EDN

Part 2 of Cooley survey shows SystemC use declinging; SystemVerilog increasing

Hey folks, John Cooley’s posted on deepchip.com Part 2 of his IC verification census, which features data indicating that SystemC use is decreasing while SystemVerilog use is increasing and that ...
EDN

The war is over: C++ and SystemC coexist in a single flow

Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this ...
Electronics Weekly

Hardware design and simulation tools to use SystemC language

CoWare has developed tools for hardware design and simulation centred around the SystemC language. Called ConvergenSC, the software is said to be faster than the reference simulator for SystemC ...
Semiconductor Engineering

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Electronic Design

SystemC Closes The C-To-RTL Gap

With a new version 2.1 and its emphasis on transaction-level modeling, SystemC is finding its role as the glue that binds architectural analysis and the RTL implementation world. When the SystemC ...
Semiconductor Engineering

Speeding Up Verification Using SystemC

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about ...